A semiconductor device typically includes a plurality of layers of circuit patterns formed on a substrate, and an alignment mark for positioning or alignment is formed in a mark formation area of a predetermined, layer of the substrate so as to accurately align the circuit patterns of the plurality of layers relative to each other, in a production step of the semiconductor device. In a case that the substrate is a semiconductor wafer (hereinafter referred to simply as “wafer”), the alignment mark is referred to also as a “wafer mark”.
Conventionally, the minutest circuit, pattern of the semiconductor device is formed, for example, with a dry or liquid immersion lithography step using a dry or liquid immersion exposure apparatus of which exposure wavelength is 193 nm. It is expected that formation of a circuit pattern more minute, for example, than a 22 nm node is difficult even by combining the conventional photolithography and the double-patterning process which has been recently developed.
In view of this situation, it has been suggested using the directed self-assembly (directed self-organization) of a block copolymer between patterns formed by using the lithography step so as to generate a minute structure of nano-scale (sub-lithography structure), thereby forming a circuit pattern more minute than the resolution limit of the current lithography technique (see, for example, the specification of U.S. Patent Application Publication No. 2010/0297847 or Japanese Patent Application Laid-open No. 2010-269304). The patterned structure of the block copolymer is also known as a micro domain (micro phase-separated domain) or simply as a domain. The graphoepitaxy is known as a method for generating the directed self-assembly.